`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 19:55:27
// Design Name: 
// Module Name: Digits_dynamic_display_hardware_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Digits_dynamic_display_hardware_test(
        input wire clk100m,
        output wire EN3_ht, 
        output wire EN2_ht, 
        output wire EN1_ht, 
        output wire EN0_ht,
        output wire a_ht,
        output wire b_ht,
        output wire c_ht,
        output wire d_ht,
        output wire e_ht,
        output wire f_ht,
        output wire g_ht,
        output wire dp_ht
    );
    
    assign dp_ht = 1;
    /*
    assign EN3_ht = 0;
    assign EN2_ht = 1;
    assign EN1_ht = 1;
    assign EN0_ht = 1;
    assign a_ht = 0;
    assign b_ht = 0;
    assign c_ht = 1;
    assign d_ht = 0;
    assign e_ht = 1;
    assign f_ht = 1;
    assign g_ht = 1;
    */
    
    Digits_dynamic_display digits_dynamic_display(
        .clk100(clk100m),
        .AN3(4'b0000),
        .AN2(4'b0001),
        .AN1(4'b0010),
        .AN0(4'b0011),
        .EN3(EN3_ht),
        .EN2(EN2_ht),
        .EN1(EN1_ht),
        .EN0(EN0_ht),
        .a(a_ht),
        .b(b_ht),
        .c(c_ht),
        .d(d_ht),
        .e(e_ht),
        .f(f_ht),
        .g(g_ht)
    );
endmodule
